1. Field of the Invention
The present invention relates in general to the field of electronic device testing, and more particularly to a method and system for capture and compression of test data applied to an electronic device for subsequent analysis.
2. Description of the Related Art
Advances in electronic device design and fabrication have resulted in a steady pace of improvements in the speed at which electronic devices process information and the quantity of information that electronic devices are able to process. For instance, processing devices, such as personal computer central processing units (CPUs), are fabricated with smaller and more densely placed transistors to allow a greater number of transistors in a smaller integrated circuit that operate at greater clock speeds. Similar fabrication techniques applied to storage devices, such as random access memory (RAM) and flash memory, provide increased storage in a given size of a memory integrated circuit and allow access to stored information at greater clock speeds. The improved operational speeds of electronic devices have led to the development of buses that transfer information between electronic devices at increased clock speeds to result in computer systems that have enhanced overall performance. For example, double data rate (DDR) RAM provides information reads and writes on both edges of a clock to allow more rapid accesses and storage by a CPU.
One difficulty with improved electronic device performance is that electronic device designs that provide improved performance generally do so with greater design complexity. The more complex an electronic device design becomes, the greater the likelihood that errors will occur in the development of the device, either in the design or the fabrication of the electronic device. Design and fabrication errors are typically identified and then corrected by applying test data to the electronic device and determining if application of the test data provides an expected output. When a response to a test stimulus varies from the expected response, test engineers attempt to isolate and debug the design or fabrication bug that produced the erroneous response. In order to thoroughly test an electronic device, test engineers generally attempt to pass large quantities of information through the electronic device. For instance, memory test systems generate vectors of test data that are written to a test memory integrated circuit or module and then read from the test memory to compare against the written test data. Vector generator test systems rapidly produce large quantities of test data to increase the probability of locating errors. Typically, a logic analyzer analyzes the test data to identify errors that occur so that test engineers may attempt to debug the errors.
Although rapid application of large quantities of test data by a vector generator test system improves the likelihood of generating errors compared with more directed test data generation involving smaller data quantities, the large quantities of data involved with vector generators often make isolation of the source of the error and debugging of the error a difficult task. For instance, generation of a particular error sometimes requires many iterations of data that have complex interactions on the electronic device, with erroneous data sometimes left unused within the electronic device for a number of cycles before its use results in an error response. Often such errors occur intermittently so that a certain percentage of electronic devices suffer from the error while other electronic devices operate normally. In such instances, if the electronic device is in or near production, manufacturers will sometimes continue with production while the error is debugged. Before electronic devices are shipped, the manufacturer sorts out devices with the known bug by running the test vectors on each produced electronic device that detect the bug and then discarding those electronic devices that manifest the error under test. However, the test vectors that generate errors are often long and complex, with a large quantity of test data passed across the electronic device to produce the error. The precise portion of the test vector that generated the bug is often difficult to identify since, over the course of its operation, a given test vector may intermittently effect data at a given location of the electronic device, making the identification of the specific portions of the test vector that generated the error the equivalent of finding a needle in a haystack. Further, since test vectors often involve large quantities of data, only recent history of the test vector and electronic device state are typically available for analysis. The generation of the test vectors and application of the test vector data to the electronic device to sort faulty devices during commercial production thus may consume a considerable amount of time resulting in substantially slower production of the electronic device.